1. Field of the Invention
The present invention relates to a double integral type A/D converter for converting an analog signal into a digital signal and, more particularly, to a double integral type A/D converter for use with an electronic weighing system.
2. Description of the Prior Art
In an electronic weighing system required to have a high accuracy, the double integral type analog-to-digital converter (which will be shortly referred to as the "A/D converter") has been used as a converter for converting an analog signal into a digital signal.
Before entering into a detailed description of the present invention, a cursory review will be made of the prior art with reference to FIGS. 1 and 2 of the accompanying drawings.
An A/D converter capable of having an unknown input integration period changed freely by a computer has been proposed to have a structure as shown in FIG. 1. In FIG. 1: reference letter A denotes a buffer; letter B an integrator; letter C a comparator; letter D a zero crossing detector; letter E a flip-flop; letter F a counter; letter G a CPU (i.e., Central Processing Unit); and letter H an inverter and letter I an AND gate.
The operations of the circuit thus composed will be described with reference to the timing chart of FIG. 2.
When a start signal for starting the integration is output at a time t.sub.1 from the CPU G, the counter F is cleared by the output signal inverted by the inverter H, and a switch S.sub.1 is turned on to input an unknown input voltage V.sub.IN through the buffer A to the integrator so that the integration of the unknown input voltage V.sub.IN is started [as depicted by a waveform (b)] in FIG. 2. Simultaneously with this, the flip-flop E is set to output a signal H (at a High level) from its Q terminal [as depicted by a waveform (c) in FIG. 2]. Here, the flip-flop E is so constructed that it is set and reset when the input signal falls from the H (high) level to an L (low) level.
At a time t.sub.2 when the unknown input voltage integration period terminates, the start signal from the CPU G takes the H level [as depicted by a waveform (a)] of FIG. 2 so that the switch S.sub.1 is turned off whereas a switch S.sub.2 is turned on to input a reference voltage V.sub.ref through the buffer A to the integrator B. At this instant, the count is started to generate an output in a reference voltage inverse-integrator mode from the integrator B.
Here, the double integral type A/D converter is equipped with a correction circuit for correcting the offset of a system including the integrator B. This correction circuit is constructed to feed back the output of the comparator C, which is connected with the output of the integrator B, back to the integrator B. If the count is stopped at a time t.sub.3 so that the operation changes into a mode for correcting the offset of the integrator B, the comparator C enters into an oscillation mode in which its output oscillates between the "H" and "L" levels [as depicted by a waveform (e)] of FIG. 2.
If this oscillatory state is caused, the output of the comparator C cannot be directly input to the flip-flop E which is made operative to control the switching of the integration modes--because the flip-flop E may possibly have its reset and set terminals active simultaneously. With this in mind, therefore, there has been connected to the output of the comparator C the zero crossing detector D which is composed of a multi-vibrator, a logical operation circuit and so on, so that a one shot pulse is output at the time t.sub.3 and input to the flip-flop E for switching the modes of the integrator B [as depicted by a waveform (g)] of FIG. 2.
As a result, the flip-flop E is reset to input its output pulses as a zero crossing signal from its Q terminal to the CPU G [as depicted by the waveform (g)] of FIG. 2.
Thus, the double integral type A/D converter of the prior art is accompanied by a problem in that it requires the zero crossing detector having such a complicated circuitry as to increase the number of its parts and raise its fabrication cost.
Since, in the offset mode, the input level of the integrator does not correspond to the offset voltage of the buffer connected upstream of the integrator, there arises another problem in that an auto-zero capacitor C.sub.0 connected with the other input of the integrator is not accurately charged with the offset voltage of the whole system including the buffer, the integrator and the comparator.
In another aspect, the A/D converter having the structure thus far described is suitably used with electronic weighing systems of various types having coarse to fine accuracies and can find remarkably wide applications. Therefore, an attempt has been made to assemble the A/D converter into a single package so that the number of steps of assembly on the production line may be reduced while the quality of the package is improved.
In the single package of the prior art, however, there has been used a hybrid IC (i.e., Integrated Circuit), which is prepared, for example, by forming a circuit pattern on a ceramic substrate, by connecting circuit elements such as resistors, capacitors, transistors and/or semiconductor elements with the circuit pattern, and by molding those circuit elements with a silicon resin, an epoxy resin or the like. Despite this structure, however, the hybrid IC is accompanied by the following problems:
(1) Because of lower heat resistance, the hybrid IC has to be held at a lower temperature during the temperature test for the final product than a monolithic IC so that it cannot be temperature tested over a wider range. In other words, the hybrid IC cannot be burned in under the same conditions as the monolithic IC.
(2) The single package using the hybrid IC cannot be as small as that using a monolithic IC.
(3) Since the single package using the hybrid IC is simply coated, its heat resistance becomes liable to deterioration by cracking, if any, thereby to producing inferior products.